William RickertandClaude Opus 5
49ad7e97cf
Parsed the pin-definition tables out of both datasheets - Table 2-1-1 (CH32L103, C8T6 column) and Table 2 (STM32F103, LQFP48 column) - and diffed them pin by pin. Zero mismatches, including OSC_IN/OSC_OUT, NRST, PA11/PA12 for USB, PA13/PA14 for SWD, and BOOT0. Power pins differ only in naming. This was the one unverified assumption the whole project rested on: three boards laid out to a footprint that has to accept either MCU. It holds. Full table recorded in Documents/pinout-L103-vs-F103.md. Co-Authored-By: Claude Opus 5 <[email protected]>
49 lines
2.4 KiB
Markdown
49 lines
2.4 KiB
Markdown
# Documents
|
|
|
|
Diagrams, the BOM, and the datasheets for parts this design actually depends on.
|
|
|
|
## Diagrams
|
|
|
|
| File | Shows |
|
|
|---|---|
|
|
| `three-board-overview.svg` | All three boards at the same key spacing |
|
|
| `half-left-staggered.svg` | Left half — 34 keys, six clean columns |
|
|
| `half-right-staggered.svg` | Right half — 41 keys |
|
|
| `numpad-layout.svg` | Numpad — 25 keys plus the volume encoder |
|
|
| `104-key-split.svg` | How a full 104 maps across the three boards |
|
|
| `half-left.svg`, `half-right.svg` | The earlier row-staggered split, kept for reference |
|
|
|
|
`bom.csv` carries LCSC part numbers, JLC basic/extended status and the
|
|
swap-dependent parts. `pinout-L103-vs-F103.md` is the 48-pin overlay that
|
|
validates the dual-MCU footprint.
|
|
|
|
## Datasheets
|
|
|
|
Only the parts this design depends on. The wider WCH collection — including the
|
|
CH32X035 and CH32V203 docs used to rule out crystal-less USB — lives in
|
|
`~/Documents/Projects/WCH CH ICs/`.
|
|
|
|
| File | Part | Why it's here |
|
|
|---|---|---|
|
|
| `CH32L103DS0.PDF` | CH32L103C8T6 | The MCU. Pinout, 64 K flash / 20 K SRAM, HSI accuracy table (§3.3.6), USBFS with 8 device endpoints (§1.4.20). |
|
|
| `CH32L103RM.PDF` | CH32L103C8T6 | Reference manual. USB clock path (§3.3.5.6), `RB_UC_DEV_PU_EN` internal 1.5 kΩ D+ pull-up, HSICAL/HSITRIM. |
|
|
| `CH334DS1.PDF` | CH334R | The hub. Variant feature table (which packages expose `PSELF` and port power switching), crystal-free caveats (§6.2), and the CH213 reference design for VBUS protection. |
|
|
| `STM32F103x8xB_datasheet_rev1.PDF` | STM32F103C8T6 | The pin-compatible escape-hatch MCU. Source for the LQFP48 pin overlay, now done — see `pinout-L103-vs-F103.md`. |
|
|
|
|
## ⚠️ The STM32F103 copy is Rev 1 (preliminary)
|
|
|
|
st.com refuses scripted download (HTTP/2 reset on curl; its CSP also blocks
|
|
exfiltrating a browser-side fetch). This copy came from a third-party mirror and
|
|
is the **early preliminary revision, 65 pages** — the current one is Rev 20 at
|
|
~117 pages.
|
|
|
|
For the LQFP48 pin numbering it is fine, and the overlay has now been done against it: that table has not changed since 2007,
|
|
and PC13/PC14/PC15, OSC_IN/OSC_OUT, NRST, PA11/PA12, PA13/PA14 and BOOT0 are all
|
|
present and verified in this copy.
|
|
|
|
**Do not trust it for anything electrical** — absolute maximums, timings, current
|
|
consumption and errata have all moved since Rev 1. For those, pull the current
|
|
datasheet by hand from
|
|
<https://www.st.com/resource/en/datasheet/stm32f103c8.pdf> in a browser and
|
|
replace this file.
|